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- Towards Semi-automatic Generation of R2R MappingsPublication . Pequeno, Valéria M.; Vidal, Vânia M. P.; Vinuto, Tiago da SilvaTranslating data from linked data sources to the vocabulary that is expected by a linked data application requires a large number of mappings and can require a lot of structural transformations as well as complex property value transformations. The R2R mapping language is a language based on SPARQL for publishing expressive mappings on the web. However, the specification of R2R mappings is not an easy task. This paper therefore proposes the use of mapping patterns to semi-automatically generate R2R mappings between RDF vocabularies. In this paper, we first specify a mapping language with a high level of abstraction to transform data from a source ontology to a target ontology vocabulary. Second, we introduce the proposed mapping patterns. Finally, we present a method to semi-automatically generate R2R mappings using the mapping patterns.
- Effect of Fused Filament Fabrication Processing Parameters on The Mechanical Properties of PLA ComponentsPublication . Marat-Mendes, R.; Guedes, M.; Leite, M.; Baptista, R.This paper studies the influence of Fused Filament Fabrication processing parameters upon mechanical properties and microstructural features of processed PLA parts. The effect of extrusion temperature and raster angle were tested upon two PLA filaments of different trademarks, DoWire and BQ, using a commercial fused deposition extruder. The filling density, layer thickness and velocity were kept constant at 60 %, 0.2 mm and 40 mm/s, respectively. Results allowed to determine fused filament fabrication parameters resulting in increased mechanical performance of manufactured parts. Mechanical performance is higher when material is stored under controlled atmosphere before use, and when material deposition direction is aligned with applied load. Increasing the extrusion temperature also increases performance, by increasing deformation ability of PLA molecules. Obtained results contribute to accumulation of a property database and provide design guidance to the procurement of additive manufacturing products with enhanced mechanical strength.
- Experimental and Numerical Characterization of Stress-Strain Fields on Sandwich Beams, Subjected to 3PB and 4PBPublication . Marat-Mendes, R.; Martins, R.; Reis, L.
- LIF and SFS techniques for early detection of biofilms harmful for cultural heritagePublication . Utkin, A.B.; Chaves, Paulo; Fernades, L.; I.V., Pinto; Revez, M.J.Specific LIF (laser induced fluorescence) and SFS (spectral fluorescence signature) sensors have been developed for detecting biofilms colonizing the surface of cultural heritage artefacts. The sensors contribute to a large-scale monitoring and decision supporting system, which is being deployed for historical monument protection within the framework of the European project STORM.
- Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC SizingPublication . Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.
- Layout-Aware Challenges and a Solution for the Automatic Synthesis of RadioFrequency IC BlocksPublication . Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.
- New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing OptimizationPublication . Lourenço, N.; Martins, R.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches that are based on sorting, the distance between elements determines the probability of decisions taken during optimization. Three implementations of those ideas were tried in AIDA's NSGAII evolutionary kernel, and successfully used in the optimization of a Voltage Controlled Oscillator and a Low Noise Amplifier with pre-optimized inductor sets obtained using the SIDeO toolbox, showing their strengths when compared to previous state-of-the-art mapping strategies.
- Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo SimulationsPublication . Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.This paper presents an efficient yield optimization approach using k-means clustering algorithm to reduce Monte Carlo (MC) simulations. This approach uses a commercial electrical simulator and PDK models for evaluation purposes. The method was integrated in an analog IC design flow that includes the AIDA-C circuit sizing optimization tool. The proposed yield estimation technique reduces the number of required MC simulations during the optimization process. The simulated solutions are the most likely to populate the Pareto optimal front and result from a selection process based on a modified k-means algorithm. The proposed approach leads 75% reduction in the total number of the MC simulations for the presented case study
- Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware ApproachPublication . Passos, F.; Castro Lópes, R.; Roca, E.; Fernándes, F.; Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing re-design iterations if they are not considered by the designer. To avoid this problem, and reduce the design time, this paper presents a systematic design of a VCO, entailing layout parasitics and accurate characterization of passive components from early design stages. Results clearly illustrate the benefit of this strategy.
- Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC CircuitsPublication . Póvoa, R.; Canelas, A.; Martins, R.; Lourenço, N.; Horta, N.; Goes, J.his paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.