Percorrer por autor "Horta, Nuno"
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- DeepPlacer: A Custom Integrated OpAmp Placement Tool using Deep ModelsPublication . Gusmão, António; Póvoa, Ricardo; Horta, Nuno; Lourenço, Nuno; Martins, RicardoMechanisms towards the automatic analog integrated circuit layout design have been an intensive research topic in the past few decades. Still, the industrial environment has no automatic approach established. The advances of machine learning applications in electronic design automation come with the promise to change this reality. This paper proposes a deep learning generative model for the placement ‘‘optimization’’ of analog integrated circuit basic blocks. The model behaves as an argmin operator for the placement cost function and can provide placement solutions instantly. Moreover, the model can be fed with unlabeled data, greatly facilitating data collection. A generic and innovative circuits’ representation at the network’s input layer is proposed, encoding the devices’ dimensions, connectivity, and topological constraints. Besides, the randomness found in generative models is embedded directly into the feature vector, as the order of the features per device is shuffled in the input vector. Shuffling the order of the devices’ features in the input not only brings multi-modality but also solves a generalization problem, as there is not any natural order defined to place devices in the feature vector. As a proof of concept, a deep artificial neural network capable of proposing different placement solutions, in less than 150 ms each, for six amplifier topologies and, in multiple technology nodes ranging from 350 nm down to 65 nm, is demonstrated. DeepPlacer was capable of producing correct solutions for topologies and technology nodes not present in the training set, showing good generalization while not hindering circuit performance due to the placement
- FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based AlgorithmsPublication . Canelas, António; Póvoa, Ricardo; Martins, Ricardo; Lourenço, Nuno; Guilherme, Jorge; Carvalho, João Paulo; Horta, NunoThis paper presents fuzzy c-means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy c-means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a k-means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy
- A new family of CMOS inverter based OTAs for Biomedical and Healthcare ApplicationsPublication . Póvoa, Ricardo; Canelas, António; Martins, Ricardo; Lourenço, Nuno; Horta, Nuno; Goes, JoãoThis paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages.
- Shortening the Gap between Pre- and Post-Layout Analog IC Performance by Reducing the LDE-induced Variations with Multi-Objective Simulated Quantum AnnealingPublication . Martins, Ricardo; Lourenço, Nuno; Póvoa, Ricardo; Horta, NunoThe design of analog and mixed-signal integrated circuits (ICs) is intricate due to the continuous nature of the signals handled. Still, it is also strongly affected by the physical implementation of analog devices on the circuits’ layout. The circuit layout corresponds to the physical implementation of an analog IC used in fabrication that describes its devices geometrically. As circuits’ integration and device sizes shrink, the physics of the interactions between devices, as they are placed in the layout, was proved to easily drive analog and mixed-signal ICs from promising pre-layout performances to completely post-layout malfunction. As these layout-dependent effects (LDEs) can only be evaluated once the layout is completed, the true post-layout performance is only evaluated in a late stage of the traditional design flow, causing expensive redesign iterations lacking the information that identifies precisely where, in the layout, there are problems needed to be solved. For technologies above the 40-nanometers, the leading causes of LDEs are mobility and threshold voltage variations. This paper proposes an automatic device placement methodology that explicitly accounts for, and minimizes, these LDEs. An absolute representation of the floorplan is adopted, and, multiple optimization techniques, including the novel, constrained archive-based multi-objective implementation of the simulated quantum annealing inspired algorithm, enhanced with specific LDE-impact mitigation operators are applied to solve the problem. In each of these optimization processes, established LDE formulations for accurate circuit simulation models are used to evaluate each candidate placement solution, and, guide the optimization process. In the case of multi-objective implementations, ultimately offering a realistic perspective of the LDE-aware design tradeoffs between performance deterioration and used chip area. Experimental results conducted over state-of-the-art analog structures on a challenging 65-nanometers technology node show that the proposed methodology shortens the gap between pre- and post-layout performance by reducing the LDE-induced variations, aiming for first-time-right layout design
- A Sub-1 µA Low-Power, LowNoise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential SignalsPublication . Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Lourenço, Nuno; Póvoa, RicardoThis paper presents the design of a low-power low-noise amplifier for biomedical and healthcare applications, focusing on lectromyography and electrooculography. The signals operate in different broad bands, yet follow an impulse-shape transmission, being suitable to be applied and detected by the same receiver. The biopotential sensing amplifiers usually have a major impact in power and noise performance of an analog front end; hence, the development of a low-noise amplifier with low-power consumption is of great importance. In this paper, the state-of-the-art amplifiers for biomedical applications are overviewed, and the proposed solution is presented. The proposed design has tunable cutoff frequency (FC) and gain, being adjustable for each type of signal. The circuit is designed in UMC 130 nm CMOS technology, supplied by 1.2 V, and consumes less than 1 μA. Post-layout simulation results show that, at the high FC of 2 kHz, the gain is 34 dB, presenting an input-referred noise of 1.476 μVrms corresponding to a noise efficiency factor (NEF) of 1.27. Whereas at the low FC of 20.91 Hz, the gain is 52.35 dB, the input-referred noise is 0.202 μVrms, and the NEF is 1.70.
- A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential SignalPublication . Vieira, Rafael; Näf, Fabian; Martins, Ricardo; Horta, Nuno; Lourenço, N.; Póvoa, RicardoThis paper presents a low-noise inverter-based current-mode instrumentation amplifier with tunable gain and bandwidth for electromyogram (EMG) and electrooculogram (EOG) biopotential signals, targeting low input noise while maintaining low power consumption. The gain tuning method is based on pseudo-resistors, whereas the bandwidth is tunable due to a varactor system that is controlled by the same control voltage that tunes the gain. The circuit was designed and manufactured using the 110 nm UMC CMOS technology node, occupying an area of 0.624 mm2. The circuit presents a functioning mode for each biopotential signal with different characteristics, for the EMG a gain of 34.7 dB and a bandwidth of 1412 Hz was measured, with an input referred noise of 1.407 μV which matches a noise efficiency factor of 1.44. The EOG mode achieves a 39.5 dB gain and a 22.4 Hz bandwidth while presenting an input-referred noise of 0.829 μV corresponding to a noise efficiency factor of 6.37. For both modes, the supply voltage is 1.2 V and the circuit consumes 1 μA.
- Tunable Low-Power Low-Noise Amplifier for Healthcare ApplicationsPublication . Vieira, Rafael; Horta, Nuno; Póvoa, Ricardo; Lourenço, NunoThis book consists of the research, design and implementation, from sizing to layout with parasitic extraction and yield estimation, of a low-power, low-noise amplifier for biomedical and healthcare applications of bio-potential signals, particularly focusing on the electromyography and electrooculography.