Browsing by Author "Horta, N."
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- Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC CircuitsPublication . Póvoa, R.; Canelas, A.; Martins, R.; Lourenço, N.; Horta, N.; Goes, J.his paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.
- Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC SizingPublication . Canelas, A.; Martins, R.; Póvoa, R.; Lourenço, N.; Horta, N.This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.
- A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency ApplicationsPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.The topic of this brief is a ingle-stage amplifier biased by a doublet of voltage-combiners in a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining proper dc biasing and avoiding the need of any device stacking. The topology has been automatically designed, optimized, and laid out, from sizing to layout level, using a layout-aware approach provided by the AIDA framework, a state-of-the-art analog IC design optimization framework. Experimental results prove that a gain of approximately 44 dB, together with a figure-of-merit higher than 1300 MHz × pF/mW are achievable using the proposed topology, with standard UMC 130 nm technology devices and a 1.2-V supply source. Finally, an extension to supply sources below nominal is explored, showing exciting results toward a future of high energy-efficiency amplifiers.
- Layout-Aware Challenges and a Solution for the Automatic Synthesis of RadioFrequency IC BlocksPublication . Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed tool exploits the full capabilities of most established computer-aided design tools available nowadays, i.e., off-the-shelf circuit simulator, electromagnetic simulator and layout extractor. The approach intends to bypass the two major bottlenecks of RF-design: the design of reliable integrated inductors and accurate layout parasitic estimates since the early stages of design process.
- A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain.Publication . Póvoa, R.; Horta, N.; Goes, J.
- New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing OptimizationPublication . Lourenço, N.; Martins, R.; Póvoa, R.; Canelas, A.; Horta, N.; Passos, F.; Castro López, R.; Roca, E.; Fernández, F.This paper presents new indexing and mutation operators, in the context of bottom-up hierarchical multi-objective optimization of radio frequency integrated circuits, for pre-optimized sets of solutions from the hierarchical sub-levels when moving up in hierarchy. Two ideas, one based on a Voronoi decomposition and another based on the nearest neighborhood, are explored, where, and unlike previous approaches that are based on sorting, the distance between elements determines the probability of decisions taken during optimization. Three implementations of those ideas were tried in AIDA's NSGAII evolutionary kernel, and successfully used in the optimization of a Voltage Controlled Oscillator and a Low Noise Amplifier with pre-optimized inductor sets obtained using the SIDeO toolbox, showing their strengths when compared to previous state-of-the-art mapping strategies.
- Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current StarvingPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents an improved single-stage amplifier biased by voltage-combiners, through the proper usage of current starving. The topology designed and fabricated shows an enhancement of the low-frequency gain, an improvement in the establishing time due to enhanced gain-bandwidth product, and a high improvement of the energy efficiency. The circuit was optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint analog IC sizing and optimization tool, and simulation results demonstrate that a gain above 60 dB and a figure-of-merit over 900 MHz×pF/mA are acquirable with this circuit, using the UMC 130-nm technology design kit. The circuit was fabricated and experimentally measured, presenting a gain of 58 dB with a figure-of-merit of 1102 MHz×pF/mA, for a 3.3 V supply source.
- Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency EnhancementPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a dc gain above 47 dB and a figure-of-merit better than 960 MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130-nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6 MHz*pF/mA.
- Sub- μW Tow-Thomas Based Biquad Filter with Improved Gain for Biomedical ApplicationsPublication . Póvoa, R.; Arya, R.; Canelas, A.; Passos, F.; Martins, R.; Lourenço, N.; Horta, N.This paper presents an innovative topology of a gm-C Operational Transconductance Amplifier (OTA), with improved gain and energy-efficiency and its corresponding implementation inside a second order Tow-Thomas based filter configuration, for biomedical and healthcare applications. The proposed OTA architecture takes advantage of a current division technique, as well as the usage of a pair of cross-coupled voltage-combiners in replacement of the static current source that traditionally bias the differential pair. The circuitry proposed in this paper is described at analytical level, fully-designed at sizing level and validated at simulation level compounded by Monte Carlo results, using a standard 130 nm technology node. Both the OTA and the biquad filter architecture are compared, in terms of performance indexes, with state-of-the-art bibliography, where the potential of both is demonstrated. The designed filter operates at weak inversion and sub-threshold, being supplied by a 0.9 V source, achieving a cut-off frequency of 15 Hz, a gain of 7 dB, hence improving the input-referred noise and consuming nearly 0.55 μW.
- Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware ApproachPublication . Passos, F.; Castro Lópes, R.; Roca, E.; Fernándes, F.; Martins, R.; Lourenço, N.; Póvoa, R.; Canelas, A.; Horta, N.This paper focuses on the systematic design of voltage controlled oscillators (VCO), a commonly used radiofrequency (RF) electronic circuit. RF circuits are among the most difficult analog circuits to design due to its trade-offs and high operation frequencies. At such operation frequencies, layout parasitics and accurate passive component characterization become of upmost importance, causing re-design iterations if they are not considered by the designer. To avoid this problem, and reduce the design time, this paper presents a systematic design of a VCO, entailing layout parasitics and accurate characterization of passive components from early design stages. Results clearly illustrate the benefit of this strategy.