Percorrer por autor "Silva-Pereira, Marco"
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- Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLsPublication . Silva-Pereira, Marco; Vaz, J. CaldinhasThe power optimisation at circuit level of a high-speed counter and aretiming circuit aimed for ultra-low-power digital phase-locked-loops(PLLs) is presented. The high-speed counter topology is based on awell-known asynchronous type with a precise sampling phase genera-tor. Different types of custom true single-phase clock (TSPC) logicstyle are briefly revised and then strategically used. It is shown that aparticular TSPC flip-flop when operating as a retiming element canachieve optimal power efficiency. A prototype was fabricated in anearlier generation 0.13 μm CMOS technology and characterised witha 1 V supply. Measurements show a state-of-the-art power consump-tion of about 48 μW when operating with a 2.4 GHz input signal.
- A Single-Ended Modified Class-E PA With HD2 Rejection for Low-Power RF ApplicationsPublication . Silva-Pereira, Marco; Caldinhas Vaz, J.This letter presents a fully integrated single-ended power amplifier for ultralow-power applications. The single-ended configuration is possible due to a choke-inductor less output network capable of rejecting the second-harmonic emission. A switching duty-ratio lower than 50% avoids the impedance transformation output network traditionally required for proper class-E operation. At 2.45 GHz, the PA (including the driver) delivers 1.4 dBm to a 50 Ω load and achieves an overall efficiency of 51% while complying with the spurious emission regulation. The prototype was fabricated in 0.13 μm CMOS.