Browsing by Author "Goes, J."
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- Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC CircuitsPublication . Póvoa, R.; Canelas, A.; Martins, R.; Lourenço, N.; Horta, N.; Goes, J.his paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.
- A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency ApplicationsPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.The topic of this brief is a ingle-stage amplifier biased by a doublet of voltage-combiners in a folded configuration, in order to be supplied by a power source of 1.2 V, maintaining proper dc biasing and avoiding the need of any device stacking. The topology has been automatically designed, optimized, and laid out, from sizing to layout level, using a layout-aware approach provided by the AIDA framework, a state-of-the-art analog IC design optimization framework. Experimental results prove that a gain of approximately 44 dB, together with a figure-of-merit higher than 1300 MHz × pF/mW are achievable using the proposed topology, with standard UMC 130 nm technology devices and a 1.2-V supply source. Finally, an extension to supply sources below nominal is explored, showing exciting results toward a future of high energy-efficiency amplifiers.
- A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain.Publication . Póvoa, R.; Horta, N.; Goes, J.
- Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current StarvingPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents an improved single-stage amplifier biased by voltage-combiners, through the proper usage of current starving. The topology designed and fabricated shows an enhancement of the low-frequency gain, an improvement in the establishing time due to enhanced gain-bandwidth product, and a high improvement of the energy efficiency. The circuit was optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint analog IC sizing and optimization tool, and simulation results demonstrate that a gain above 60 dB and a figure-of-merit over 900 MHz×pF/mA are acquirable with this circuit, using the UMC 130-nm technology design kit. The circuit was fabricated and experimentally measured, presenting a gain of 58 dB with a figure-of-merit of 1102 MHz×pF/mA, for a 3.3 V supply source.
- Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency EnhancementPublication . Póvoa, R.; Lourenço, N.; Martins, R.; Canelas, A.; Horta, N.; Goes, J.This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a dc gain above 47 dB and a figure-of-merit better than 960 MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130-nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6 MHz*pF/mA.