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Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits

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dc.contributor.authorPóvoa, R.
dc.contributor.authorCanelas, A.
dc.contributor.authorMartins, R.
dc.contributor.authorLourenço, N.
dc.contributor.authorHorta, N.
dc.contributor.authorGoes, J.
dc.date.accessioned2025-02-18T15:55:12Z
dc.date.available2025-02-18T15:55:12Z
dc.date.issued2017
dc.description.abstracthis paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationR. Póvoa, A. Canelas, R. Martins, N. Lourenço, N. Horta and J. Goes, "A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits," 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos - Taormina, Italy, 2017, pp. 121-124pt_PT
dc.identifier.doi10.1109/PRIME.2017.7974122pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.26/54463
dc.language.isoengpt_PT
dc.publisherIEEEpt_PT
dc.titleDynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuitspt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.endPage124pt_PT
oaire.citation.startPage121pt_PT
oaire.citation.title3th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Giardini Naxos - Taormina, Italy.pt_PT
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT

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