Percorrer por autor "Vaz, J. Caldinhas"
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- A 1.1 µA voltage reference circuit with high PSRR and temperature compensationPublication . Pereira, M. Silva; Costa, João E. N.; Santos, M.; Vaz, J. CaldinhasThis paper presents a low-power and a low output voltage CMOS Bandgap Reference Generator topology with high PSRR and a novel temperature curvature compensation method. The proposed design was implemented in a standard 0.13 μm CMOS process. The main circuit is based in an opamp based β-multiplier bandgap circuit with resistive division. The compensation method cancels out up to 2nd order non-linear terms of the BJT voltage by using the MOSFET leakage current effect. The performance of the circuit was verified by post-layout simulations. Simulated results have shown temperature coefficients as low as -4.4 ppm/°C over a temperature range of 140°C (-40°C to 100°C). In addition the circuit demonstrated a PSSR of -100 dB at low frequencies and -73 dB at 1 MHz. The current consumption is 1.1 μA at 27°C.
- A 1.7-mW −92-dBm Sensitivity Low-IF Receiver in 0.13-um CMOS for Bluetooth LE ApplicationsPublication . Silva-Perreira, Marco.; Sousa, J. T. de; Freire, J. Costa; Vaz, J. CaldinhasThis paper presents a 1.7-mW low-intermediate-frequency receiver design for Bluetooth low-energy (BLE) applications. The design exploits particular aspects of BLE, such as the relaxed in-band interference characteristics, more precisely the C/I1 MHz, and the relatively high-frequency-shift keying modulation index, to deliver a high level of energy efficiency and simplicity to the receiver baseband architecture. Reliable quadrature signals are generated in the RF signal path without consuming energy, which is supported by an inverter-based low-noise amplifier (LNA) that achieves high gain and low noise figure under low-power budgets. A small-signal analysis of low-power inverter-based LNAs is presented offering simple design equations. Seeking an affordable solution, the fabricated prototype is fully integrated into an earlier generation CMOS technology node (0.13 μm), occupying a silicon area smaller than 0.7 mm2. The receiver achieves a sensitivity level of -92 dBm while consuming 1.41 mA from a 1.2-V supply.
- Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLsPublication . Silva-Pereira, Marco; Vaz, J. CaldinhasThe power optimisation at circuit level of a high-speed counter and aretiming circuit aimed for ultra-low-power digital phase-locked-loops(PLLs) is presented. The high-speed counter topology is based on awell-known asynchronous type with a precise sampling phase genera-tor. Different types of custom true single-phase clock (TSPC) logicstyle are briefly revised and then strategically used. It is shown that aparticular TSPC flip-flop when operating as a retiming element canachieve optimal power efficiency. A prototype was fabricated in anearlier generation 0.13 μm CMOS technology and characterised witha 1 V supply. Measurements show a state-of-the-art power consump-tion of about 48 μW when operating with a 2.4 GHz input signal.