Browsing by Author "Vaz, J. Caldinhas"
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- A 1.1 µA voltage reference circuit with high PSRR and temperature compensationPublication . Pereira, M. Silva; Costa, João E. N.; Santos, M.; Vaz, J. CaldinhasThis paper presents a low-power and a low output voltage CMOS Bandgap Reference Generator topology with high PSRR and a novel temperature curvature compensation method. The proposed design was implemented in a standard 0.13 μm CMOS process. The main circuit is based in an opamp based β-multiplier bandgap circuit with resistive division. The compensation method cancels out up to 2nd order non-linear terms of the BJT voltage by using the MOSFET leakage current effect. The performance of the circuit was verified by post-layout simulations. Simulated results have shown temperature coefficients as low as -4.4 ppm/°C over a temperature range of 140°C (-40°C to 100°C). In addition the circuit demonstrated a PSSR of -100 dB at low frequencies and -73 dB at 1 MHz. The current consumption is 1.1 μA at 27°C.
- Power optimization of both a high-speed counter and a retiming element for 2.4 GHz digital PLLsPublication . Silva-Pereira, M.; Vaz, J. CaldinhasThe power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.