Power optimization of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs

Silva-Pereira, M.; Vaz, J. Caldinhas

http://hdl.handle.net/10400.26/54332

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Authors

Silva-Pereira, M.

Vaz, J. Caldinhas

Abstract(s)

The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.

URI

http://hdl.handle.net/10400.26/54332

Citation

Silva‐Pereira, M., & Caldinhas Vaz, J. (2018). Power optimisation of both a high‐speed counter and a retiming element for 2.4 GHz digital PLLs. Electronics Letters, 54(5), 284-285.