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Power optimization of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs

2018-03-01Journal article Restricted access
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dc.contributor.authorSilva-Pereira, M.
dc.contributor.authorVaz, J. Caldinhas
dc.date.accessioned2025-02-10T10:55:44Z
dc.date.available2025-02-10T10:55:44Z
dc.date.issued2018-03-01
dc.description.abstractThe power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationSilva‐Pereira, M., & Caldinhas Vaz, J. (2018). Power optimisation of both a high‐speed counter and a retiming element for 2.4 GHz digital PLLs. Electronics Letters, 54(5), 284-285.pt_PT
dc.identifier.doihttps://doi.org/10.1049/el.2017.4391pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.26/54332
dc.language.isoengpt_PT
dc.relation.publisherversionhttps://ietresearch.onlinelibrary.wiley.com/doi/10.1049/el.2017.4391pt_PT
dc.titlePower optimization of both a high-speed counter and a retiming element for 2.4 GHz digital PLLspt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.citation.endPage285pt_PT
oaire.citation.issue5pt_PT
oaire.citation.startPage284pt_PT
oaire.citation.titleElectronics Letterspt_PT
oaire.citation.volume54pt_PT
rcaap.rightsclosedAccesspt_PT
rcaap.typearticlept_PT

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