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Shortening the Gap between Pre- and Post-Layout Analog IC Performance by Reducing the LDE-induced Variations with Multi-Objective Simulated Quantum Annealing

dc.contributor.authorMartins, Ricardo
dc.contributor.authorLourenço, Nuno
dc.contributor.authorPóvoa, Ricardo
dc.contributor.authorHorta, Nuno
dc.date.accessioned2025-05-26T15:15:45Z
dc.date.available2025-05-26T15:15:45Z
dc.date.issued2021-02
dc.description.abstractThe design of analog and mixed-signal integrated circuits (ICs) is intricate due to the continuous nature of the signals handled. Still, it is also strongly affected by the physical implementation of analog devices on the circuits’ layout. The circuit layout corresponds to the physical implementation of an analog IC used in fabrication that describes its devices geometrically. As circuits’ integration and device sizes shrink, the physics of the interactions between devices, as they are placed in the layout, was proved to easily drive analog and mixed-signal ICs from promising pre-layout performances to completely post-layout malfunction. As these layout-dependent effects (LDEs) can only be evaluated once the layout is completed, the true post-layout performance is only evaluated in a late stage of the traditional design flow, causing expensive redesign iterations lacking the information that identifies precisely where, in the layout, there are problems needed to be solved. For technologies above the 40-nanometers, the leading causes of LDEs are mobility and threshold voltage variations. This paper proposes an automatic device placement methodology that explicitly accounts for, and minimizes, these LDEs. An absolute representation of the floorplan is adopted, and, multiple optimization techniques, including the novel, constrained archive-based multi-objective implementation of the simulated quantum annealing inspired algorithm, enhanced with specific LDE-impact mitigation operators are applied to solve the problem. In each of these optimization processes, established LDE formulations for accurate circuit simulation models are used to evaluate each candidate placement solution, and, guide the optimization process. In the case of multi-objective implementations, ultimately offering a realistic perspective of the LDE-aware design tradeoffs between performance deterioration and used chip area. Experimental results conducted over state-of-the-art analog structures on a challenging 65-nanometers technology node show that the proposed methodology shortens the gap between pre- and post-layout performance by reducing the LDE-induced variations, aiming for first-time-right layout designeng
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationRicardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta, Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing, Engineering Applications of Artificial Intelligence,pt_PT
dc.identifier.doi10.1016/j.engappai.2020.104102
dc.identifier.issn0952-1976
dc.identifier.urihttp://hdl.handle.net/10400.26/57875
dc.language.isoengpt_PT
dc.peerreviewedyes
dc.publisherElsevierpt_PT
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/
dc.subjectAnalog and mixed-signal integrated circuits
dc.subjectAutomatic layout generation
dc.subjectElectronic design automation
dc.subjectLayout-dependent effects
dc.subjectMulti-objective optimization
dc.subjectSimulated annealing
dc.subjectSimulated quantum annealing
dc.titleShortening the Gap between Pre- and Post-Layout Analog IC Performance by Reducing the LDE-induced Variations with Multi-Objective Simulated Quantum Annealingeng
dc.typejournal article
dspace.entity.typePublication
oaire.citation.titleEngineering Applications of Artificial Intelligencept_PT
oaire.citation.volume98pt_PT
oaire.versionhttp://purl.org/coar/version/c_970fb48d4fbd8a85
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT

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