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Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing

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dc.contributor.authorCanelas, A.
dc.contributor.authorMartins, R.
dc.contributor.authorPóvoa, R.
dc.contributor.authorLourenço, N.
dc.contributor.authorHorta, N.
dc.date.accessioned2025-02-18T16:23:26Z
dc.date.available2025-02-18T16:23:26Z
dc.date.issued2017
dc.description.abstractThis paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.pt_PT
dc.description.versioninfo:eu-repo/semantics/publishedVersionpt_PT
dc.identifier.citationA. Canelas, R. Martins, R. Póvoa, N. Lourenço and N. Horta, "Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, Switzerland, 2017, pp. 1201-1206pt_PT
dc.identifier.doi10.23919/DATE.2017.7927171pt_PT
dc.identifier.urihttp://hdl.handle.net/10400.26/54471
dc.language.isoengpt_PT
dc.publisherIEEEpt_PT
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/7927171pt_PT
dc.titleEfficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizingpt_PT
dc.typeconference object
dspace.entity.typePublication
oaire.citation.endPage1206pt_PT
oaire.citation.startPage1201pt_PT
oaire.citation.titleDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, Switzerland.pt_PT
rcaap.rightsclosedAccesspt_PT
rcaap.typeconferenceObjectpt_PT

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