Repository logo
 
Publication

Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling

dc.contributor.authorVieira, R.
dc.contributor.authorPassos, F.
dc.contributor.authorPóvoa, R.
dc.contributor.authorMartins, R.
dc.contributor.authorHorta, N.
dc.contributor.authorGuilherme, J.
dc.contributor.authorLourenço, N.
dc.date.accessioned2025-09-18T13:12:34Z
dc.date.available2025-09-18T13:12:34Z
dc.date.issued2022
dc.description.abstractThis work presents a study of two analog frontend circuit architectures for heartbeat detection. Both circuits present an amplification block as the first stage, followed by a band-pass filter. In the first, the heartbeat detection is done using an adaptive threshold based on pulse-width, whereas the heartbeat detection in the second is done using a sample and hold to find the maximum and minimum peak of each beating. Both architectures are modeled in Verilog-A and simulated using real-world ECG signals with different characteristics. This work studies possible fundamental analog circuit blocks suitable for wearable implementation. It evaluates critical performances requirements from the analysis of the behavior simulations. It was verified that the first circuit can properly detect heartbeats as long as the input-referred noise is below 21 μV, whereas the second one ensures it until 30 μV. The low cutoff frequency can be approximately 10 Hz without compromising the signal’s peaks, which means that these specifications can be relaxed substantially compared to systems intended to reconstruct the signal accurately.eng
dc.identifier.citationR. Vieira et al., "Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling," 2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Villasimius, Italy, 2022, pp. 1-4
dc.identifier.doi10.1109/SMACD55068.2022.9816253
dc.identifier.urihttp://hdl.handle.net/10400.26/58719
dc.language.isoeng
dc.peerreviewedyes
dc.publisherIEEE
dc.relation.hasversionhttps://ieeexplore.ieee.org/document/9816253
dc.rights.urihttp://creativecommons.org/licenses/by-nc/4.0/
dc.subjectHeartbeat Detection
dc.subjectHealthcare
dc.subjectVerilog-A
dc.titleArchitectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modelingeng
dc.typeconference proceedings
dspace.entity.typePublication
oaire.citation.conferenceDate2022-12-06
oaire.citation.conferencePlaceVillasimius, Itália
oaire.citation.endPage4
oaire.citation.startPage1
oaire.citation.titleProceedings - 2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2022
oaire.versionhttp://purl.org/coar/version/c_970fb48d4fbd8a85

Files

Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
Architectural_Design_for_Heartbeat_Detection_Circuits_using_Verilog-A_Behavioral_Modeling.pdf
Size:
1.53 MB
Format:
Adobe Portable Document Format
License bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
1.85 KB
Format:
Item-specific license agreed upon to submission
Description: