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A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

2023-02-06Journal article Open access
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dc.contributor.authorFerlini, Frederico
dc.contributor.authorViel, Felipe
dc.contributor.authorSeman, Laio Oriel
dc.contributor.authorHector Pettenghien
dc.contributor.authorBezerra, Eduardo
dc.contributor.authorLEITHARDT, VALDERI
dc.date.accessioned2023-03-17T10:40:07Zen
dc.date.available2023-03-17T10:40:07Zen
dc.date.issued2023-02-06en
dc.date.updated2023-02-09T10:44:31Z
dc.description.abstractThe increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.pt_PT
dc.description.versionN/Apt_PT
dc.identifier.doi10.3390/electronics12040807pt_PT
dc.identifier.slugcv-prod-3138217
dc.identifier.urihttp://hdl.handle.net/10400.26/44198en
dc.language.isoengpt_PT
dc.peerreviewedyespt_PT
dc.relationResearch Center for Endogenous Resource Valorization
dc.relationCOPELABS - Cognitive and People-centric Computing R&D Unit
dc.subjectSETpt_PT
dc.subjectfault injectionpt_PT
dc.subjectLEON3pt_PT
dc.subjectFPGApt_PT
dc.subjectspace applicationspt_PT
dc.subjectCAPpt_PT
dc.titleA Methodology for Accelerating FPGA Fault Injection Campaign Using ICAPpt_PT
dc.typejournal article
dspace.entity.typePublication
oaire.awardTitleResearch Center for Endogenous Resource Valorization
oaire.awardTitleCOPELABS - Cognitive and People-centric Computing R&D Unit
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F05064%2F2020/PT
oaire.awardURIinfo:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F04111%2F2020/PT
oaire.citation.titleElectronicspt_PT
oaire.fundingStream6817 - DCRRNI ID
oaire.fundingStream6817 - DCRRNI ID
person.familyNameFerlini
person.familyNameViel
person.familyNameSeman
person.familyNameBezerra
person.familyNameREIS QUIETINHO LEITHARDT
person.givenNameFrederico
person.givenNameFelipe
person.givenNameLaio Oriel
person.givenNameEduardo
person.givenNameVALDERI
person.identifierJsOq45sAAAAJ&hl=pt-PT
person.identifier.ciencia-id0614-5834-E7F3
person.identifier.orcid0000-0002-9550-1822
person.identifier.orcid0000-0002-0972-2160
person.identifier.orcid0000-0002-6806-9122
person.identifier.orcid0000-0001-9177-5503
person.identifier.orcid0000-0003-0446-9271
person.identifier.ridH-2402-2018
person.identifier.scopus-author-id55608292500
person.identifier.scopus-author-id6506097045
person.identifier.scopus-author-id35303109600
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.identifierhttp://doi.org/10.13039/501100001871
project.funder.nameFundação para a Ciência e a Tecnologia
project.funder.nameFundação para a Ciência e a Tecnologia
rcaap.cv.cienciaid0614-5834-E7F3 | Valderi Reis Quietinho LeithardtPT
rcaap.rightsopenAccesspt_PT
rcaap.typearticlept_PT
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