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Browsing by Author "Silva-Pereira, M."

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  • Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors
    Publication . Silva-Pereira, M.; Assunção, Mário; Vaz, João Caldinhas
    Current-mode class-D (CMCD) power amplifiers (PAs) may not achieve a switching efficiency as good as class-E PAs, but they require fewer inductances and deliver almost five times more power for the same load and supply voltage when compared with the ideal push–pull class-E PA. Furthermore, CMCD PAs can easily use bondwires as the only circuit inductors, a precious feature that Internet-of-Things (IoT) wireless interfaces can exploit. For this reason, we analyze the voltage and current waveforms in CMCD PAs without assuming infinite value feeding inductors (i.e., without choke inductors). It is shown that the current stress on the switching device is significantly higher than in the conventional topology, especially in bondwire-based designs where relatively small feeding induc tances are presented. Finally, we propose a design procedure for a given feeding inductance that maximizes energy efficiency while delivering a compact-size solution. A 2.4-GHz PA capable of delivering 19.8 dBm to a 100-Ω differential load with a power added-efficiency (PAE) of 58% is presented. Three-dimensional electromagnetic (3-D EM) simulations combined with postlayout simulations were used to evaluate the PA performance in a quad-flat nonlead (QFN)-type package. The circuit is designed in a 0.13-μm process and only occupies a silicon area of 0.025 mm2.
    2020-05Journal article Restricted access Show more
  • Power optimization of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs
    Publication . Silva-Pereira, M.; Vaz, J. Caldinhas
    The power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.
    2018-03-01Journal article Restricted access Show more