Póvoa, R.Lourenço, N.Martins, R.Canelas, A.Horta, N.Goes, J.2025-02-182025-02-182018R. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. C. G. Horta and J. Goes, "Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 3, pp. 266-270.http://hdl.handle.net/10400.26/54459This brief presents the design of a single-stage amplifier with enhanced gain and speed, without the need for using any cascode devices, positive feedback, or feed forward technique. Instead, two voltage-combiners replace the traditional tail current source, commonly employed to bias the differential pair. The resultant topology shows both additional dc gain and a gain bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a dc gain above 47 dB and a figure-of-merit better than 960 MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130-nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6 MHz*pF/mA.engjournal article10.1109/TCSII.2017.2686586